Programmable logic devices (PLDs) are a well-known type of programmable integrated circuit (IC) that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles comprise various types of logic blocks, which can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), bus or network interfaces such as Peripheral Component Interconnect Express (PCIe) and Ethernet and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Partial reconfiguration has made it possible to reduce the power consumed and the size of circuits implemented on programmable ICs. Using partial reconfiguration, it is possible to dynamically change a portion of a circuit in response to changes in operating conditions, while keeping other portions of the circuit running. However, current design tools are limited to supporting the development of static designs, which are designs that have a fixed physical topology. For example, in a static design there is a one-to-one mapping between design elements and FPGA resources.
Developing partial reconfiguration designs using current tools is cumbersome and prone to error. To create a partial reconfiguration design, the designer creates a static design that contains instantiations of empty (black-box) modules to represent the reconfigurable regions. Each reconfigurable region corresponds to a portion of a configuration bitstream that implements the design, with that portion being filled (perhaps multiple times) at runtime using partial bitstreams for reconfigurable modules. For each reconfigurable region, the designer creates constraints that define a set of physical design resources in order to define the bounds of the reconfigurable region. Each reconfigurable module is an element that may occupy a reconfigurable region during runtime, with different reconfigurable modules occupying the reconfigurable region at different times. The designer creates and adds decoupling blocks to surround the reconfigurable regions. Each decoupling block ensures that a signal leaving (and on occasion, entering) a reconfigurable region takes on a known, safe, value during the “reconfiguration interval,” which is the period of time when the reconfigurable module in a reconfigurable region is being replaced by another reconfigurable module. The designer creates a set of designs in which each design represents one reconfigurable module that can be inserted into the static portion of the design at run time. The designer must ensure that identical interfaces and names are maintained for all the reconfigurable modules targeted for a reconfigurable region. The reconfigurable modules and static portion of the design are synthesized independently, and the designer creates a set of configurations in which each configuration is a fully populated static design including the static portion and a reconfigurable module placed in each reconfigurable region. Special commands are used to link the reconfigurable modules to the appropriate reconfigurable regions in the different configurations.